1. Technical Field
The present disclosure relates to semiconductor chip stack devices. It more generally relates to the creation of an electric connection between two stacked chips.
2. Description of the Related Art
In chip stack devices, semiconductor chips or wafers are stacked. The chips are for example appended with their front or back sides against each other, or one's front side against the other's back side, and are interconnected. This assembly mode especially enables an increase in the number of functions carried out by the device without increasing the occupied surface area. Although chip assemblies will be mentioned in the present description, it should be clear that said chips may be plates, semiconductor wafers, or elements of semiconductor wafers.
FIG. 1 is a perspective view schematically showing a step of assembly of two semiconductor chips, respectively 1 and 2, of a chip stack device. In this example, chips 1 and 2 have their front sides against each other. Connecting elements 10 are arranged in an array of rows and columns formed on the front side of chip 1. A corresponding array of connecting elements 20, of the same pitch, is formed on the front side of chip 2. Connecting elements 10 and 20 are, for example, copper pads or pillars. On assembly of the chips, each connecting element 10 of chip 1 comes into contact with the connecting element 20 of chip 2.
During the actual assembly step, chips 1 and 2 are pressed against each other and attached, for example by molecular bonding or by soldering of connecting elements 10 onto connecting elements 20. The issue of aligning chips 1 and 2 appears in this step. The alignment must be sufficiently accurate to ensure for each connecting element 10 of chip 1 to be positioned, at least partially, in front of the corresponding connecting element 20 of chip 2, so that an electric connection can be created between the two connecting elements 10 and 20. Thus, the alignment inaccuracy margin must be smaller than the width of the connecting element. In the shown example, chip 2, is of a larger surface area than chip land comprises corners or guide marks 14′ to make the alignment easier.
The current tendency of decreasing connecting element dimensions and increasing the number of connecting elements per surface area unit makes this alignment operation particularly critical. As an illustration, connecting elements having a width ranging between 1 and 5 μm, or even smaller, can now be formed. Now, the machines used to assemble chips currently have an alignment inaccuracy margin on the order of 10 μm. A better accuracy could possibly be obtained, however causing in return an undesirable increase in assembly times and manufacturing costs.
FIG. 2 is a cross-sectional view of the chip stack device of FIG. 1 after assembly. In the shown example, chips 1 and 2 have not been properly aligned. As a result, connecting element 10a of chip 1, instead of being in contact with the corresponding connecting element 20a of chip 2, are in contact with neighboring connecting element 20b. Further, some peripheral connecting elements 10c of chip 1 (to the right of the drawing) are in contact with no connecting elements 20 of chip 2, and some peripheral connecting elements 20a of chip 2 (to the left of the drawing) are in contact with no connecting elements 10 of chip 1. Such a device will not operate correctly. Generally, the alignment issue is one of the main factors limiting the efficiency of chip stack device manufacturing chains, especially when connecting elements of small dimensions are used.